The present invention relates to the field of interconnect structures for integrated circuit packages, and in particular, to an interconnect structure for electrically connecting two electronic components and a method of making the same.
In the semiconductor industry, an integrated circuit (IC) device must be connected to a lead frame or some other support structure to produce a complete IC package. Technology has recently produced more powerful devices which can be packaged more densely. However, as the size of the devices decreases, new problems arise associated with connecting the devices to the lead frames or other support structures.
An integrated circuit is usually fabricated on a semiconductor wafer which has a number of bond pads on its surface which connect to various components of the circuit. The bond pads are connected to a wire or other electrically conductive device to permit utilization of the IC. Common methods of connecting a device to a lead frame or other support device are wire bonding, Tape Automated Bonding (TAB), Controlled Collapse Chip Connection (C4) or bump bonding, and the use of conductive adhesives.
Aluminum bond pads are the semiconductor industry standard, but a significant problem with their use is the rapid formation of a tenacious nonconductive oxide on the surface of the metal, even at room temperature. When an interconnect is made to the bond pad, the nonconductive oxide causes the interconnect to have an extremely high contact resistance. The resistance typically ranges from hundreds to millions of ohms.
In an effort to reduce the contact resistance, a noble metal, such as gold, has been used to provide an inert, oxide-free surface on the bond pad. The presence of gold on the bond pad precludes the formation of nonconductive metal oxides at the surface of the contact. However, the gold plating of a semiconductor die is an elaborate process that can be very difficult, expensive and time consuming. Another disadvantage to the use of gold is that gold and aluminum react to form an intermetallic mixture, known in the art as xe2x80x9cpurple plaguexe2x80x9d, which is a poor conductor and interferes with the electrical functioning of the circuit.
Other methods of solving this problem have involved scraping the bond pad to remove oxide immediately before the interconnect is formed, or use of a barrier layer on the bond pad. Known barrier layer materials include nickel, copper, cobalt, palladium, platinum, silver, titanium, tungsten, tin, and chromium. Many of these materials, however, also form nonconductive oxides, or have poor electrical or thermal conductivity, or a high thermal expansion. In addition, the plating processes for these materials may be complicated. Palladium plating, for example, requires both a zincate process and a plating process.
There is needed, therefore, a conductive barrier layer for use on the bond pads of an integrated circuit die that will not oxidize to form a nonconductive material. A conductive barrier layer material having good electrical conductivity, good thermal conductivity, and low thermal expansion is also needed, as well as a simple process for forming such a conductive barrier layer on the metal layer of bond pads.
The present invention provides an interconnect structure comprising a multi-layered metal bond pad on the surface of a semiconductor die. The outermost surface of the bond pad is a conductive ruthenium electrode that protects an underlying conductive layer from oxidation due to exposure to ambient environmental conditions. An electrical interconnect structure such as a wire or solder ball bump may be placed directly on the ruthenium layer in order to connect the semiconductor die to a lead frame or circuit support structure. Also provided is an electrolytic plating method for forming the ruthenium electrode of the present invention.
Advantages and features of the present invention will be apparent from the following detailed description and drawings which illustrate preferred embodiments of the invention.